Synthesis Interview Questions

• What are the various factors that need to be considered while choosing a technology library for a design?
• When stated as 0.13μm CMOS technology, what does 0.13 represent?
• What is Synthesis?
  
• What happens when a process neither has sensitivity list nor a wait statement?
  
• Where should you declare the index that is used in a for loop? What is its visibility?
  
• What are the three weak strength values in IEEE 9 valued logic?
  
• What is the difference between a transaction and an event?
  
• What is a Moore machine? How is it different from a Mealy machine?
• Assume that variable a is integer and b is natural. When are the following statements valid?

a := a + b;
b := a + 3;

• What modeling technique will decompose designs hierarchically?
• Do variables need time queues?
  
• Does simulation time advance during delta cycles?
  
• Is it true that synthesis transformations take less time at the top abstraction levels?
  
• Is it true that synthesis transformations give refined results at the top abstraction levels?
  
• What will a well formed case statement synthesize to?
  
• What will happen to a design that is synthesized without any constraints?
  
• Explain what role the Synopsys DesignWare libraries fulfill in the synthesis process.
  
• What is the difference between a high level synthesis tool (as represented by Synopsys behavioral Compiler) versus a logic synthesis tool (as represented by Synopsys Design Compiler)?
  
• Explain what it meant for Synopsys DesignWare component to be ‘inferred’ by a synthesis tool?

• What are different power reduction techniques?
  
• How do you perform Synthesis activities in Multi vt libraries?
  
• What are the advantages of clock gating?
  
• One circuit will be given to you, where one of the inputs X have a high toggling rate in the circuit. What steps you take to reduce the power in that given circuit?
  
• You will be told to realize a Boolean equation. The next question is how efficient usage of power is achieved in that crcuit?
  
• Some circuit will be given to you and will be instructed to set certain timing exceptions commands on that particular path.
  
• What is the difference in PT timing analysis during post and pre layout designs?
  
• What you mean by FSM States?
  
• Draw the timing waveforms for the circuit given?
  
• What is Setup time and hold time effects on the circuit behavior while providing different situations?
  
• What is the difference of constraints file in Pre layout and post layout?
  
• What is SPEF? Have you used it? How you can use it?
  
• What difference you found (or can find) in the netlist and your timing behavior, while performing timing analysis in pre layout and post layout?
  
• What is clock uncertainty, clock skew and clock jitter?
  
• What is the reason for skew and jitter?
  
• What is clock tree synthesis?
  
• What are the timing related commands with respect to clock?
  
• In front end, you set ideal network conditions on certain pins/clocks etc. Why? In Back end how is it taken care?
  
• Which library you have used?
  
• What difference you (can) find in TSMC and IBM libraries?
  
• Draw the LSSD cell structure in TSMC and IBM libraries?
  
• Every tool has some drawbacks? What drawbacks you find in Prime time?
  
  
• What are the difference you find when you switch from 130nm to 90nm?
  
• Explain the basic ASIC design flow? Where your work starts from? What is your role?
• What is 90nm technology means?
  
• What are the issues you faced in your designs?
  
• Perform the setup and hold check for the given circuit.
  
• Why setup and hold required for a flop?
  
• You had any timing buffer between synthesis and P&R? How much should be the margin?
  
• What are the inputs for synthesis and timing analysis from RTL and P&R team? Whether any inputs for changing the scripts?
  
• How will you fix the setup and hold violation?
  
• What are the constraints you used for the synthesis? Who decides the constraints?
  
• What is uncertainty?
  
• What is false path and multi cycle path? Give examples? For given example for false path what you will do for timing analysis?
  
• What strategies used for the power optimization for your recent project?
  
• Why max and min capacitance required?
  
• You have two different frequency for launch (say 75Mhz) and capture (say 100Mhz).
• What will happen to data? Write the waveform? If hold problem what you will do?
  
• What is Metastability? How to overcome metastability? If metastable condition exists which frequency you will use as clock- faster or slower? Why?
  
• Have you used formality? For a given block what checks it will do? How it verifies inside the block?
  
• If you changed the port names during the synthesis how will you inform Formality?
  
• Why you use power compiler? What is clock gating? What are advantage and disadvantages of clock gating? Write the clock gating circuit? Explain.
  
• How will you control the clock gating inference for block of register? Write the command for the same?
  
• Write the total power equation? What is leakage power? Write equation for it.
  
• For clock gated flop and non clock gated flop outputs connected to a AND gate what problem can you expect? How to avoid the problem?
  
• Write the sequence detector state which detects 10? How will optimize? write the verilog code for the same?
  
• What is jitter? Why it will come? How to consider? What is the command for that?
  
• What is clock latency? How to specify? What is the command for that?
  
• What is dynamic timing analysis? What is the difference with static timing analysis? Which is accurate? Why it is accurate?
  
• Give any example for Dynamic timing analysis? Do you know anything about GCL simulation?
  
• What is free running clock?
  
• What type of operating condition you consider for post layout timing analysis?
  
• What is one-hot encoding technique? What are advantages? What are types of encoding?
  
• Which scripting language you know?
  
• How will you analysis the timing of different modes in design? How many modes you had in your design? What are the clock frequencies?
  
• What your script contains?
  
• Write the digital circuit for below condition: "when ever data changes from one to zero or zero to one the circuit should generate a pulse of one clock period length"?
  
• Have come across any design with latches? What is the problem in timing analysis if you have latch in your design?
  
• Have you come across any multiple clock design? What are the issues in multiple clock designs?
  
• What you mean by synthesis strategies?

CMOS Design Interview Questions

Below are the important VLSI CMOS interview questions. This set of interview questions may be updated in future. Answers will be posted one by one as and when i prepare them ! Readers are encouraged to post answers in comment section. Here we go.........

Draw Vds-Ids curve for an MOSFET. How it varies with a) increasing Vgs b)

velocity saturation c)Channel length modulation d)W/L ratio.

What is body effect? Write mathematical expression? Is it due to parallel or serial connection of MOSFETs?

What is latch-up in CMOS design and what are the ways to prevent it?

What is Noise Margin? Explain with the help of Inverter.

What happens to delay if you increase load capacitance?

Give the various techniques you know to minimize power consumption for CMOS logic?

What happens when the PMOS and NMOS are interchanged with one another in an inverter?

What is body effect?

Why is NAND gate preferred over NOR gate for fabrication?

What is Noise Margin? Explain the procedure to determine Noise Margin

Explain sizing of the inverter?

How do you size NMOS and PMOS transistors to increase the threshold voltage?

What happens to delay if we include a resistance at the output of a CMOS circuit?

What are the limitations in increasing the power supply to reduce delay?

How does Resistance of the metal lines vary with increasing thickness and increasing length?

What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus?

Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?

Give the expression for CMOS switching power dissipation?

Why is the substrate in NMOS connected to ground and in PMOS to VDD?

What is the fundamental difference between a MOSFET and BJT ?

Which transistor has higher gain- BJT or MOS and why?

Why PMOS and NMOS are sized equally in a Transmission Gates?

What is metastability? When/why it will occur? What are the different ways to avoid this?

Explain zener breakdown and avalanche breakdown?

* What happens if Vds is increased over saturation?

In the I-V characteristics curve, why is the saturation curve flat or constant?

What happens if a resistor is added in series with the drain in a CMOS transistor?

What are the different regions of operation in a CMOS transistor?

What are the effects of the output characteristics for a change in the beta (β) value?

What is the effect of body bias?

What is hot electron effect and how can it be eliminated?

What is channel length modulation?

What is the effect of temperature on threshold voltage?

What is the effect of temperature on mobility?

What is the effect of gate voltage on mobility?

What are the different types of scaling?

What is stage ratio?

What is charge sharing on a bus?

What is electron migration and how can it be eliminated?

Can both PMOS and NMOS transistors pass good 1 and good 0? Explain.

Why is only NMOS used in pass transistor logic?

What are the different methodologies used to reduce the charge sharing in dynamic logic?

What are setup and hold time violations? How can they be eliminated?

Explain the operation of basic SRAM and DRAM.

Which ones take more time in SRAM: Read operation or Write operation? Why?

What is meant by clock race?

What is meant by single phase and double phase clocking?

If given a choice between NAND and NOR gates, which one would you pick? Explain.

Explain the origin of the various capacitances in the CMOS transistor and the physical reasoning behind it.

Why should the number of CMOS transistors that are connected in series be reduced?

What is charge sharing between bus and memory element?

What is crosstalk and how can it be avoided?

Realize an XOR gate using NAND gate.

What are the advantages and disadvantages of Bi-CMOS process?

Draw an XOR gate with using minimum number of transistors and explain the operation.

What are the critical parameters in a latch and flip-flop?

What is the significance of sense amplifier in an SRAM?

Explain Domino logic.

What are the advantages of depletion mode devices over the enhancement mode devices?

How can the rise and fall times in an inverter be equated?

What is meant by leakage current?

Realize an OR gate using NAND gate.

Realize an NAND gate using a 2:1 multiplexer.

Realize an NOR gate using a 2:1 multiplexer.

Draw the layout of a simple inverter.

What are the substrates of PMOS and NMOS transistors connected to and explain the results if the connections are interchanged with the other.

What are repeaters?

What is tunneling problem?

What is meant by negative biased instability and how can it be avoided?

What is Elmore delay algorithm?

What is meant by metastability?

What is the effect of Vdd on delay?

What is the effect of delay, rise and fall times with increase in load capacitance?

What is the value of mobility of electrons?

What is value of mobility of holes?

Give insights of an inverter. Draw Layout. Explain the working.

* Give insights of a 2 input NOR gate. Draw Layout. Explain the working.

Give insights of a 2 input NAND gate. Draw layout. Explain the working?

Implement F= not (AB+CD) using CMOS gates.

What is a pass gate. Explain the working?

Why do we need both PMOS and NMOS transistors to implement a pass gate?

What does the above code synthesize to?

Draw cross section of a PMOS transistor.

Draw cross section of an NMOS transistor.

What is a D-latch?

Implement D flip-flop with a couple of latches?

Implement a 2 input AND gate using transmission gate?

Explain various adders and difference between them?

How can you construct both PMOS and NMOS on a single substrate?

What happens when the gate oxide is very thin?

What is SPICE?

What are the differences between IRSIM and SPICE?

What are the differences between netlist of HSPICE and Spectre?

Implement F = AB+C using CMOS gates?

What is hot electron effect?

Define threshold voltage?

List out the factors affecting power consumption on a chip?

What r the phenomenon which come into play when the devices are scaled to the sub-micron lengths?

What is clock feed through?

Implement an Inverter using a single transistor?

What is Fowler-Nordheim Tunneling?

Which gate is normally preferred while implementing circuits using CMOS logic, NAND or NOR? Why?

Draw the Differential Sense Amplifier and explain its working. How to size this circuit?

What happens if we use an Inverter instead of the Differential Sense Amplifier?

Draw the SRAM Write Circuitry

How did you arrive at sizes of transistor in SRAM?

How does the size of PMOS pull up transistors for bit and bitbar lines affect SRAM’s performance?

What is the critical path in a SRAM?

Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

Give a big picture of the entire SRAM layout showing placements of SRAM cells, row decoders, column decoders, read circuit, write circuit and buffers.

In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?

Digital design Interview Questions

• If inverted output of D flip-flop is connected to its input how the flip-flop behaves?
• Design a circuit to divide input frequency by 2?
• Design a divide by two counter using D-Latch.
• Design a divide-by-3 sequential circuit with 50% duty cycle.
• What are the different types of adder implementation?
• Draw a Transmission Gate-based D-Latch?
• Give the truth table for a Half Adder. Give a gate level implementation of the same.
• Design an OR gate from 2:1 MUX.
• What is the difference between a LATCH and a FLIP-FLOP?
• Design a D Flip-Flop from two latches.
• Design a 2 bit counter using D Flip-Flop.
• What are the two types of delays in any digital system
• Design a Transparent Latch using a 2:1 Mux.
• Design a 4:1 Mux using 2:1 Mux's.
• What is metastable state? How does it occur?
• What is metastablity?
• Design a 3:8 decoder
• Design a FSM to detect sequence "101" in input sequence
• Convert NAND gate into Inverter in two different ways.
• Design a D and T flip flop using 2:1 mux only.
• Design D Latch from SR flip-flop.
• Define Clock Skew, Negative Clock Skew, Positive Clock Skew?
• What is race condition? How it occurs? How to avoid it?
• Design a 4 bit Gray Counter?
• Design 4-bit synchronous counter, asynchronous counter?
• Design a 16 byte asynchronous FIFO?
• What is the difference between a EEPROM and FLASH?
• What is the difference between a NAND-based Flash and NOR-based Flash?
• Which one is good: asynchronous reset or synchronous reset? Why?
• Design a simple circuit based on combinational logic to double the output frequency.
• What is the difference between flip-flop and latch?
• Implement comparator using combinational logic, that compares two 2-bit numbers A and B. The comparator should have 3 outputs: A > B, A < a =" B.">
• Give two ways of converting a two input NAND gate to an inverter?
• What is the difference between mealy and moore state-machines?
• What is the difference between latch based design and flip-flop based design?
• What is metastability and how to prevent it?
• Design a four-input NAND gate using only two-input NAND gates.
• Why are most interrupts active low?
• How do you detect if two 8-bit signals are same?
• 7 bit ring counter's initial state is 0100010. After how many clock cycles will it return to the initial state?
• Design all the basic gates NOT, AND, OR, NAND, NOR, XOR, XNOR using 2:1 Multiplexer.
• How will you implement a full subtractor from a full adder?
• In a 3-bit Johnson's counter what are the unused states?
• What is difference between RAM and FIFO?
• What is an LFSR? List a few of its industry applications.
• Implement the following circuits:
  (a) 3 input NAND gate using minimum number of 2 input NAND gates
  (b) 3 input NOR gate using minimum number of 2 input NOR gates
  (c) 3 input XNOR gate using minimum number of 2 input XNOR gates assuming 3 inputs A,B,C?
• Design a D-latch using (a) using 2:1 Mux (b) from S-R Latch?
• How to implement a Master Slave flip flop using a 2 to 1 mux?
• How many 2 input xor's are needed to inplement 16 input parity generator?
• Convert xor gate to buffer and inverter.
• Difference between onehot and binary encoding?
• What are different ways to synchronize between two clock domains?
• How to calculate maximum operating frequency?
• How to find out longest path?
• How to achieve 180 degree exact phase shift?
• What is significance of ras and cas in SDRAM?
• Tell some of applications of buffer?
• Implement an AND gate using mux?
• What will happen if contents of register are shifter left, right?
• What is the basic difference between analog and digital design?
• What advantages do synchronous counters have over asynchronous counters?
• What types of flip-flops can be used to implement the memory elements of a counter?
• What are the advantages of using a microprocessor to implement a counter rather than the conventional method (flip-flop and logic gates)?
• What is the principal advantage of Gray Code over straight (conventional) binary?
• What does Pipelining do?
• Design divide by 2, divide by 3 circuit with equal duty cycle.
• How many 4:1 mux do you need to design a 8:1 mux?
• What is D-Word, Q-word?
• Define Moore, Mealy state machines. Which one is good for timing?
• Design a FSM to detect 10110. What is the minimum number of flops required?
• Design a simple circuit based on combinational logic to double the output frequency.
• Design a 2bit up/down counter with clear using gates. (No verilog or vhdl)
• Design a finite state machine to give a modulo 3 counter when x=0 and modulo 4 counter when x=1.
• Minimize: S= A' + AB
• What is the function of a D-flipflop, whose inverted outputs are connected to its input?
• How to synchronize control signals and data between two different clock domains?
• Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.
• In what cases do you need to double clock a signal before presenting it to a synchronous state machine?
• How many bit combinations are there in a byte?
• What are the different Adder circuits you studied?
• Give the truth table for a Half Adder. Give a gate level implementation of the same.
• Convert 65(Hex) to Binary
• Convert a number to its two's compliment and back.
• What is the 1's and 2's complement of the decimal number 25.
• If A?B=C and C?A=B then what is the boolean operator ?

What is the difference between a latch and a flip-flop?

• Both latches and flip-flops are circuit elements whose output depends not only on the present inputs, but also on previous inputs and outputs.

• They both are hence referred as "sequential" elements.

• In electronics, a latch, is a kind of bistable multi vibrator, an electronic circuit which has two stable states and thereby can store one bit of of information. Today the word is mainly used for simple transparent storage elements, while slightly more advanced non-transparent (or clocked) devices are described as flip-flops. Informally, as this distinction is quite new, the two words are sometimes used interchangeably. [wiki]

• In digital circuits, a flip-flop is a kind of bistable multi vibrator, an electronic circuit which has two stable states and thereby is capable of serving as one bit of memory. Today, the term flip-flop has come to generally denote non-transparent (clocked or edge-triggered) devices, while the simpler transparent ones are often referred to as latches.[wiki]

• A flip-flop is controlled by (usually) one or two control signals and/or a gate or clock signal.

• Latches are level sensitive i.e. the output captures the input when the clock signal is high, so as long as the clock is logic 1, the output can change if the input also changes.

• Flip-Flops are edge sensitive i.e. flip flop will store the input only when there is a rising or falling edge of the clock.

• A positive level latch is transparent to the positive level(enable), and it latches the final input before it is changing its level(i.e. before enable goes to '0' or before the clock goes to -ve level.)

• A positive edge flop will have its output effective when the clock input changes from '0' to '1' state ('1' to '0' for negative edge flop) only.
  

• Latches are faster, flip flops are slower.

• Latch is sensitive to glitches on enable pin, whereas flip-flop is immune to glitches.

• Latches take less gates (less power) to implement than flip-flops.

• D-FF is built from two latches. They are in master slave configuration.

• Latch may be clocked or clock less. But flip flop is always clocked.

• For a transparent latch generally D to Q propagation delay is considered while for a flop clock to Q and setup and hold time are very important.

Synthesis perspective: Pros and Cons of Latches and Flip Flops

• In synthesis of HDL codes inappropriate coding can infer latches instead of flip flops. Eg.:"if" and "case" statements. This should be avoided sa latches are more prone to glitches.

• Latch takes less area, Flip-flop takes more area ( as flip flop is made up of latches) .

• Latch facilitate time borrowing or cycle stealing whereas flip flops allow synchronous logic.

• Latches are not friendly with DFT tools. Minimize inferring of latches if your design has to be made testable. Since enable signal to latch is not a regular clock that is fed to the rest of the logic. To ensure testability, you need to use OR gate using "enable"� and "scan_enable" signals as input and feed the output to the enable port of the latch. [ref]
  

• Most EDA software tools have difficulty with latches. Static timing analyzers typically make assumptions about latch transparency. If one assumes the latch is transparent (i.e.triggered by the active time of clock,not triggered by just clock edge), then the tool may find a false timing path through the input data pin. If one assumes the latch is not transparent, then the tool may miss a critical path.

• If target technology supports a latch cell then race condition problems are minimized. If target technology does not support a latch then synthesis tool will infer it by basic gates which is prone to race condition. Then you need to add redundant logic to overcome this problem. But while optimization redundant logic can be removed by the synthesis tool ! This will create endless problems for the design team.

• Due to the transparency issue, latches are difficult to test. For scan testing, they are often replaced by a latch-flip-flop compatible with the scan-test shift-register. Under these conditions, a flip-flop would actually be less expensive than a latch. Read a good article on problems of latch published in eetimes long back !!

• Flip flops are friendly with DFT tools. Scan insertion for synchronous logic is hassle free.

Home

Clock uncetainity, setup hold timing , jitter, skew,

whole VLSI world is depending on two pillars, setup time and hold time".


The doubt why is set up and hold in flip-flop always lingers in my mind. Being a digital design engineer, i should be able to go beneath transistor and convince myself the existence of setup delay and hold delay. I know metastability state of the flip flop or charging or discharging of capacitor on a CMOS, upon which all the gates, flip flops are built. When i say "i know metastability" i may know about its standard definition as per data book. If i advent into getting answer to "why metastability", i believe i must be able to understand setup time and hold time.



Let me try to dig myself. What i know? Flip flop is combination of 2 latches, and latch is level triggered. One is positive level triggered and another in negative level triggered. If so whatever data sent to two latches will be launched or captured on different edges. Then why metastability? Why set up time? Why hold time?

So how two level triggered latches form an edge triggered flop? Let me get in to the latch. After all how it works? Say one input is given...then when can i expect the output data? Is it immediately ? or does it take some time ?

If i remember working of simple SR latch from several theory classes and text books i know that any latch output doesn’t stabilize immediately. Output changes to intermediate values of 0 (or 1) then 1 (or 0) then finally it gets settles at 0 (or 1). It used to take 2 or 3 looping of data between NOR (or NAND ) gates.
So in this way it takes 2-3 data cycles....right....This must happen for both latches of flop. Hence this must take some time, may be in nano second or pico second, but it consumes some time !


Now, from the working principle of Master slave flip flop, i know that both latches won’t work together. Because i have arranged flop circuit such away that slave follows master. It means to say that when master latches the data slave sleeps, then slave follows master. Or in other words, slave releases the data which is latched earlier by the master. As i understood earlier, to latch the data, master takes 2-3 cycle. Same should be the story for slave.

Now let me extend my imagination to the next horizon.

To a flop which is exclusively designed as edge triggered with basic gates itself, may be NOR or NAND based, or may be based on CMOS full custom circuit, same of 2-3 cycle delay applies here as well. All that happens is those 2-3 cycles to stabilize data which is coming in and going out !

I should analyze practical conditions of latching the data.

Considering one internal data cycle is completed in logic gate,data is not yet stabilized within this latch. If i allow one more input to enter at the same time what will happen to that data which was under process? Naturally latch may start processing new input data or may go to unknown loop state that i think i call as metastable state ! Poor latch, it must have completely confused, whether to drop the catching of present data or should i try to catch new one? I am the boss and hence i, as a designer of latch, has instructed latch to to both, to process present data (so that it can catch it and memorize it), then look for new one. As a duty bound soldier latch will try to do both.

Same applies for data that was already latched but about to leave out of the latch. These two timing delay requirements ultimately constitute setup and hold; hold time is for time required for data to come out while setup for data to get latched. Hence, i believe, hold is always related with launch clock whereas setup is related with capture clock.

So, what I can i understand is i don’t need a reference for hold since it’s already in flop. That’s why for hold analysis, clock period is always considered as 0ns, which virtually turns out to be no clock. ( or..."hold is not dependent on clock"). This is not always true. There are exceptional cases where data is not launched at 0ns with respect to capture clock. These kind of situations should be dealt separately.

Always i must remember that flop has latch structure, this means to say, when one latch works another doesn't do any work. So if i consider register to register path, when one is launching data next one is ready to receive data. That’s all ! It continues like that way throughout the digital circuit. When first one is receiving next flop is ready to launch...and so on. To summarize, it takes one clock cycle to complete the launch or capture. That’s why we always use terms such as present data, previous data when dealing with data flow through flip flop so that i can understand the delay introduced by the flop (due to its latch architecture) which i technically termed it as setup time and hold time.

As per the definition, data should be stable at input before clock pulse ticks at the clock pin of the flip flop. I understand from the definition that data at the input should have completed the process of 2-3 cycle interchanging values at the receiving gates section of the latch to settle down to a known value. By any means, if clock is faster (or data is slower in its arrival at input), then it can tick at at the time when data might have completed its 1 or 2 cycle interchanging state. Then i am sure any one of these intermediate value can get latched, which may not the actual intended original input data.

For hold, definition is time for which data should be stable after clock edge. Once the clock edge ticks data present within latch tries to go out. I know this takes another 2-3 cycle intermediate values within latch and settle to known value at the output pin of the flip flop. Imagining that output pin is connected to input of another flip flop and there is no combinational circuit in between them, lets assume that delay is zero or very less. In this case intermediate value can immediately reflect at the input of receiving flip flop, which is functionally fatal error. Introduce a delay element which is more than 2-3 cycle delay time (i.e. hold time), then delay element provides sufficient time for the data to settle to known value.

Looking into these aspects minimum period for the clock can't be less than the addition of setup time and hold time. if clock period becomes lesser than this, i am sure flip flop will fail.

But i should be cautious in understanding that every capture flop becomes launch flop for new data to be launched. So we need to make sure that combinational delay is enough so that new data launched doesn’t kill the data which is already available within flop. And hence hold check is carried out for clock edge which is one lesser than (or previous to) setup check. Or in other words, setup check for present data which is traveling, hold for new (future) data. Present data should reach the capture flop input before capture clock reaches there.(Setup check). New data shouldn't reach too fast to capture flop so that present data doesn't corrupt.

Well...after all these literature exercise i must agree that i don't want all jargons to implement a practical design. What i need is basic understanding of setup time, hold time and how this affects or controls the timing of a timing path. It would be nice if i can fix setup and hold violations by adjusting rest of the parameters such as skew, latency and jitter.

by murali http://asic-soc.blogspot.com