We have not had great results with FreeHDL or with Green Mountain VHDL. It seems that these projects may have been
terminated. GHDL on Mac OSX uses
Wine, but works without problems.
In
Pune at the start of the month, Norman Chang, Ting-Sheng Ku, Jai
Pollayil of Apache/Ansys and NVIDIA presented and ESD check
methodologywith Fast Full-chip Static and Macro-level Dynamic Solutions
. ESD stands for Elecro-Static Discharge and is basically injecting
very high static voltages (think how your hand gets charged up sometimes
when you touch a door handle) which can destroy a chip. This is done
using three models which correspond to touching the chip with a finger
(known as the Human Body Model or HBM), touching the chip with a machine
such as manufacturing tester or an assembly machine known as the
Machine Model or MM) and touching the chip with a tool such a tweezers
or a screwdriver (known as the Charged Device Model or CDM). If the chip
passes all these tests then it can survive test, assembly and shipping.
And, after it has got to the consumer, the sort of abuse that people
walking around on carpets or wearing silk shirts can give it. The human
body model (HBM) has voltages in the KV range and the CDM has currents
in the 10A range.
Here's is one way that this is actually tested. Well, not really but
there is an element of truth in it and it is very funny:
To avoid ESD destroying the chip, various protection structures are
required that essentially route the charge away harmlessly so it doesn't
destroy the delicate gate-oxide in much the same way as a lightening
protector does for a building (with much higher voltages). The challenge
for a designer is that these structures must be verified before the
chip tapes out. Finding out a chip doesn't pass ESD tests after
manufacture is a huge problem and will require a respin.
In days gone by, ESD protection was something required only in the I/O
pads (so that they would defend the rest of the chip) but that no longer
is sufficient and ESD cells are required in the core especially for
flip-chip bumped chips where the I/Os are distributed across the die.
This means that they need to be planned into the floorplan and taken
acount of for their impact on other aspects of the design such as
timing. Thinner oxides and reduced currents before metal interconnect
acts like fuse-wire make this increasingly hard with each process
generation.
There are two parts to verification of ESD. Static verification of all
three models using test cases and block/IP level verification of the
HBM/CD. Apache's PathFinder is a tool that can handle all of this.
For static verification, performance and capacity are key in order to
perform:
Fast
full-chip layout-based checks
High-capacity and
accurate metal/via resistance extraction
Inter- and
intra-domain resistance checks
Realistic I-V model
(snapback included) for diode/clamp in
R
and current density checks
Current density and
voltage check, particularly critical for IP
Full-chip
ESD check required for identifying problems such as inter-block
connectivity related
Macro-level dynamic
ESD solution
Transistor-level stress analysis for
1M+ transistor blocks within couple of days
Consider
substrate effect, clamp modeling with snapback, metal grid RLC, and pogo
pin modeling
The dynamic verification must:
Perform diagnosis of potential failure mechanisms when
silicon failures occur
Verify robustness of the fix by comparing differential stressed values
of the failed junctions
Check potential design weaknesses of CDM events before tape-out on
analog / mixed-signal / I/O blocks
The slides from the entire presentation, including much
more detail of both PathFinder and NVIDIA's methodology are here.
