My Experience with Synthesis for clear Netlist for tower library

during synthesis i faced following problems

setup violations

hold violations

unconstrained paths

timing arcs

these are errors we have to solve during synthesis

Reason for unconstrained paths

if ur logic of RTL code is in such a way that some combinational circuit output is given as clock input to other sequential circuit then design compiler with command " check_timing" shows u unconstrained paths

Reason for timing arcs

this error comes mostly in combinational logics only , due to logic of ur RTL code

for ex: variable1 = ( some condition) ? data1 : variable1

this creates a timing arc (or timing loops) in ur generated netlist

Reason for Setup and hold violations

during synthesis one must give constrains to ur clock because their will be no ideal clock in real time

constrains include setup, hold, input delay output delay max delay transition time raise and fall time etc.. of clock default we give 20 percentage of ur clock period

How did i solve ???

• unconstrained paths i solved by changing logic of RTL , i made all unstrained path logics which are actually combinational logic to sequential logic

• timing arcs also i change the logic of RTL for example above code

for ex: variable1 = ( some condition) ? data1 : variable1

i changed to

always(data)

if(some condition )

variable1 = data1;

i dint write any where like

always(data1)

if (condition )

variable1 = data;

else

variable1 = variable1 ;

so my problem solved but by changing RTL always functionality should meet

• setup violations are more dangerous error then hold violations which must be solved during synthesis

1. try to change logic of ur code
2. try to change cells drives in netlist
3. try to avoid delay cells
4. try to reduce ur setup constrains from 20 to less then 20 percentage if it does not required much
5. if ur functionality not effects much if logic is meeting for second clock pulse then go for multicycle path
6. put false paths between two clocks if ur design using two clocks

• hold violations can be done in back end by changing RC values , but during synthesis also u can remove with command "set_fix_hold"

which automatically puts buffers in data path , if not solved put manual delay buffers in the netlist

so, i shared my experience

regards

vijay