verilig code for 10 bit full adder

module fulladd (sum, c_out, a, b, c_in);

output sum, c_out;
input a, b, c_in;
wire s1, c1, c2;

xor (s1, a, b);
and (c1, a, b);
xor (sum, s1, c_in );
and (c2, s1, c_in);
or (c_out, c1, c2);
endmodule

module nbitadder (sum, c_out, a, b, c_in);

output [9:0] sum;
output c_out;
input [9:0] a, b;
input c_in;

wire c0, c1, c2, c3, c4, c5, c6, c7, c8 ;

fulladd fa0 (sum[0], c0, a[0], b[0], c_in);
fulladd fa1 (sum[1], c1, a[1], b[1], c0);
fulladd fa2 (sum[2], c2, a[2], b[2], c1);
fulladd fa3 (sum[3], c3, a[3], b[3], c2);
fulladd fa4 (sum[4], c4, a[4], b[4], c3);
fulladd fa5 (sum[5], c5, a[5], b[5], c4);
fulladd fa6 (sum[6], c6, a[6], b[6], c5);
fulladd fa7 (sum[7], c7, a[7], b[7], c6);
fulladd fa8 (sum[8], c8, a[8], b[8], c7);
fulladd fa9 (sum[9], c_out, a[9], b[9], c8);

endmodule





**************************************************************
TESTBENCH FOR ABOVE CODE





module TB;

wire [9:0] sum;
wire c_out;
reg [9:0] a;
reg [9:0] b;
reg c_in;

nbitadder DUT (
.sum(sum),
.c_out(c_out),
.a(a),
.b(b),
.c_in(c_in)
);


initial
begin
#0
c_in = 1'b0;
a = 10'b0000111100;
b = 10'b0000111100;
#10
a = 10'b1111111110;
b = 10'b0000000001;
#10

#100 $finish ;

end



endmodule