FREE VHDL SIMULATORS

Simulator	Comment	Download from	Windows	Linux	Mac OSX
Aldec Active-HDL, Student Edition	Students only	Aldec Download page	Yes	No	No
ModelSim Altera Starter Edition	Only Altera FPGAs	Altera Quartus Web Edition	Yes	Yes	No
ISim	Only Xilinx FPGAs	Xilinx Webpack	Yes	Yes	No
Simili		SymphonyEDA website	Yes	Yes	No
GHDL	limited features; only VHDL-93	GHDL website	Yes	Yes	Yes

We have not had great results with FreeHDL or with Green Mountain VHDL. It seems that these projects may have been terminated.
GHDL on Mac OSX uses Wine, but works without problems.

Good links for ASIC designers

1. http://asicdigitaldesign.wordpress.com
2. http://asic-soc.blogspot.in

ESD Check Methodology

In Pune at the start of the month, Norman Chang, Ting-Sheng Ku, Jai Pollayil of Apache/Ansys and NVIDIA presented and ESD check methodologywith Fast Full-chip Static and Macro-level Dynamic Solutions . ESD stands for Elecro-Static Discharge and is basically injecting very high static voltages (think how your hand gets charged up sometimes when you touch a door handle) which can destroy a chip. This is done using three models which correspond to touching the chip with a finger (known as the Human Body Model or HBM), touching the chip with a machine such as manufacturing tester or an assembly machine known as the Machine Model or MM) and touching the chip with a tool such a tweezers or a screwdriver (known as the Charged Device Model or CDM). If the chip passes all these tests then it can survive test, assembly and shipping. And, after it has got to the consumer, the sort of abuse that people walking around on carpets or wearing silk shirts can give it. The human body model (HBM) has voltages in the KV range and the CDM has currents in the 10A range.

Here's is one way that this is actually tested. Well, not really but there is an element of truth in it and it is very funny:


To avoid ESD destroying the chip, various protection structures are required that essentially route the charge away harmlessly so it doesn't destroy the delicate gate-oxide in much the same way as a lightening protector does for a building (with much higher voltages). The challenge for a designer is that these structures must be verified before the chip tapes out. Finding out a chip doesn't pass ESD tests after manufacture is a huge problem and will require a respin.

In days gone by, ESD protection was something required only in the I/O pads (so that they would defend the rest of the chip) but that no longer is sufficient and ESD cells are required in the core especially for flip-chip bumped chips where the I/Os are distributed across the die. This means that they need to be planned into the floorplan and taken acount of for their impact on other aspects of the design such as timing. Thinner oxides and reduced currents before metal interconnect acts like fuse-wire make this increasingly hard with each process generation.

There are two parts to verification of ESD. Static verification of all three models using test cases and block/IP level verification of the HBM/CD. Apache's PathFinder is a tool that can handle all of this.

For static verification, performance and capacity are key in order to perform:

• Fast full-chip layout-based checks
  
  • High-capacity and accurate metal/via resistance extraction
  • Inter- and intra-domain resistance checks
  • Realistic I-V model (snapback included) for diode/clamp in
• R and current density checks
  
  • Current density and voltage check, particularly critical for IP
  • Full-chip ESD check required for identifying problems such as inter-block connectivity related
• Macro-level dynamic ESD solution
  
  • Transistor-level stress analysis for 1M+ transistor blocks within couple of days
  • Consider substrate effect, clamp modeling with snapback, metal grid RLC, and pogo pin modeling
  
  

The dynamic verification must:

• Perform diagnosis of potential failure mechanisms when silicon failures occur
• Verify robustness of the fix by comparing differential stressed values of the failed junctions
• Check potential design weaknesses of CDM events before tape-out on analog / mixed-signal / I/O blocks

The slides from the entire presentation, including much more detail of both PathFinder and NVIDIA's methodology are here.

verilig code for 10 bit full adder

module fulladd (sum, c_out, a, b, c_in);

output sum, c_out;
input a, b, c_in;
wire s1, c1, c2;

xor (s1, a, b);
and (c1, a, b);
xor (sum, s1, c_in );
and (c2, s1, c_in);
or (c_out, c1, c2);
endmodule

module nbitadder (sum, c_out, a, b, c_in);

output [9:0] sum;
output c_out;
input [9:0] a, b;
input c_in;

wire c0, c1, c2, c3, c4, c5, c6, c7, c8 ;

fulladd fa0 (sum[0], c0, a[0], b[0], c_in);
fulladd fa1 (sum[1], c1, a[1], b[1], c0);
fulladd fa2 (sum[2], c2, a[2], b[2], c1);
fulladd fa3 (sum[3], c3, a[3], b[3], c2);
fulladd fa4 (sum[4], c4, a[4], b[4], c3);
fulladd fa5 (sum[5], c5, a[5], b[5], c4);
fulladd fa6 (sum[6], c6, a[6], b[6], c5);
fulladd fa7 (sum[7], c7, a[7], b[7], c6);
fulladd fa8 (sum[8], c8, a[8], b[8], c7);
fulladd fa9 (sum[9], c_out, a[9], b[9], c8);

endmodule





**************************************************************
TESTBENCH FOR ABOVE CODE





module TB;

wire [9:0] sum;
wire c_out;
reg [9:0] a;
reg [9:0] b;
reg c_in;

nbitadder DUT (
.sum(sum),
.c_out(c_out),
.a(a),
.b(b),
.c_in(c_in)
);


initial
begin
#0
c_in = 1'b0;
a = 10'b0000111100;
b = 10'b0000111100;
#10
a = 10'b1111111110;
b = 10'b0000000001;
#10

#100 $finish ;

end



endmodule

Very Useful links

http://www.doulos.com/knowhow/

My Experience with Synthesis for clear Netlist for tower library

during synthesis i faced following problems

setup violations

hold violations

unconstrained paths

timing arcs

these are errors we have to solve during synthesis

Reason for unconstrained paths

if ur logic of RTL code is in such a way that some combinational circuit output is given as clock input to other sequential circuit then design compiler with command " check_timing" shows u unconstrained paths

Reason for timing arcs

this error comes mostly in combinational logics only , due to logic of ur RTL code

for ex: variable1 = ( some condition) ? data1 : variable1

this creates a timing arc (or timing loops) in ur generated netlist

Reason for Setup and hold violations

during synthesis one must give constrains to ur clock because their will be no ideal clock in real time

constrains include setup, hold, input delay output delay max delay transition time raise and fall time etc.. of clock default we give 20 percentage of ur clock period

How did i solve ???

• unconstrained paths i solved by changing logic of RTL , i made all unstrained path logics which are actually combinational logic to sequential logic

• timing arcs also i change the logic of RTL for example above code

for ex: variable1 = ( some condition) ? data1 : variable1

i changed to

always(data)

if(some condition )

variable1 = data1;

i dint write any where like

always(data1)

if (condition )

variable1 = data;

else

variable1 = variable1 ;

so my problem solved but by changing RTL always functionality should meet

• setup violations are more dangerous error then hold violations which must be solved during synthesis

1. try to change logic of ur code
2. try to change cells drives in netlist
3. try to avoid delay cells
4. try to reduce ur setup constrains from 20 to less then 20 percentage if it does not required much
5. if ur functionality not effects much if logic is meeting for second clock pulse then go for multicycle path
6. put false paths between two clocks if ur design using two clocks

• hold violations can be done in back end by changing RC values , but during synthesis also u can remove with command "set_fix_hold"

which automatically puts buffers in data path , if not solved put manual delay buffers in the netlist

so, i shared my experience

regards

vijay

Verilog Interview Questions

• What is the difference between $display and $monitor and $write and $strobe?
• What is the difference between code-compiled simulator and normal simulator?
• What is the difference between wire and reg?
• What is the difference between blocking and non-blocking assignments?
• What is the significance Timescale directivbe?
• What is the difference between bit wise, unary and logical operators?
• What is the difference between task and function?
• What is the difference between casex, casez and case statements?
• Which one preferred-casex or casez?
• For what is defparam used?
• What is the difference between “= =” and “= = =” ?
• What is a compiler directive like ‘include’ and ‘ifdef’?
• Write a verilog code to swap contents of two registers with and without a temporary register?
• What is the difference between inter statement and intra statement delay?
• What is delta simulation time?
• What is difference between Verilog full case and parallel case?
• What you mean by inferring latches?
• How to avoid latches in your design?
• Why latches are not preferred in synthesized design?
• How blocking and non blocking statements get executed?
• Which will be updated first: is it variable or signal?
• What is sensitivity list?
• If you miss sensitivity list what happens?
• In a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk? If yes, why? If not, why?
• In a pure sequential circuit is it necessary to mention all the inputs in sensitivity disk? If yes, why? If not, why?
• What is general structure of Verilog code you follow?
• What are the difference between Verilog and VHDL?
• What are system tasks?
• List some of system tasks and what are their purposes?
• What are the enhancements in Verilog 2001?
• Write a Verilog code for synchronous and asynchronous reset?
• What is pli? why is it used?
• What is file I/O?
• What is difference between freeze deposit and force?
• Will case always infer priority register? If yes how? Give an example.
• What are inertial and transport delays ?
• What does `timescale 1 ns/ 1 ps’ signify in a verilog code?
• How to generate sine wav using verilog coding style?
• How do you implement the bi-directional ports in Verilog HDL?
• How to write FSM is verilog?
• What is verilog case (1)?
• What are Different types of Verilog simulators available?
• What is Constrained-Random Verification ?
• How can you model a SRAM at RTL Level?