verilig code for 10 bit full adder

module fulladd (sum, c_out, a, b, c_in);

output sum, c_out;
input a, b, c_in;
wire s1, c1, c2;

xor (s1, a, b);
and (c1, a, b);
xor (sum, s1, c_in );
and (c2, s1, c_in);
or (c_out, c1, c2);
endmodule

module nbitadder (sum, c_out, a, b, c_in);

output [9:0] sum;
output c_out;
input [9:0] a, b;
input c_in;

wire c0, c1, c2, c3, c4, c5, c6, c7, c8 ;

fulladd fa0 (sum[0], c0, a[0], b[0], c_in);
fulladd fa1 (sum[1], c1, a[1], b[1], c0);
fulladd fa2 (sum[2], c2, a[2], b[2], c1);
fulladd fa3 (sum[3], c3, a[3], b[3], c2);
fulladd fa4 (sum[4], c4, a[4], b[4], c3);
fulladd fa5 (sum[5], c5, a[5], b[5], c4);
fulladd fa6 (sum[6], c6, a[6], b[6], c5);
fulladd fa7 (sum[7], c7, a[7], b[7], c6);
fulladd fa8 (sum[8], c8, a[8], b[8], c7);
fulladd fa9 (sum[9], c_out, a[9], b[9], c8);

endmodule





**************************************************************
TESTBENCH FOR ABOVE CODE





module TB;

wire [9:0] sum;
wire c_out;
reg [9:0] a;
reg [9:0] b;
reg c_in;

nbitadder DUT (
.sum(sum),
.c_out(c_out),
.a(a),
.b(b),
.c_in(c_in)
);


initial
begin
#0
c_in = 1'b0;
a = 10'b0000111100;
b = 10'b0000111100;
#10
a = 10'b1111111110;
b = 10'b0000000001;
#10

#100 $finish ;

end



endmodule

Very Useful links

http://www.doulos.com/knowhow/

My Experience with Synthesis for clear Netlist for tower library

during synthesis i faced following problems

setup violations

hold violations

unconstrained paths

timing arcs

these are errors we have to solve during synthesis

Reason for unconstrained paths

if ur logic of RTL code is in such a way that some combinational circuit output is given as clock input to other sequential circuit then design compiler with command " check_timing" shows u unconstrained paths

Reason for timing arcs

this error comes mostly in combinational logics only , due to logic of ur RTL code

for ex: variable1 = ( some condition) ? data1 : variable1

this creates a timing arc (or timing loops) in ur generated netlist

Reason for Setup and hold violations

during synthesis one must give constrains to ur clock because their will be no ideal clock in real time

constrains include setup, hold, input delay output delay max delay transition time raise and fall time etc.. of clock default we give 20 percentage of ur clock period

How did i solve ???

• unconstrained paths i solved by changing logic of RTL , i made all unstrained path logics which are actually combinational logic to sequential logic

• timing arcs also i change the logic of RTL for example above code

for ex: variable1 = ( some condition) ? data1 : variable1

i changed to

always(data)

if(some condition )

variable1 = data1;

i dint write any where like

always(data1)

if (condition )

variable1 = data;

else

variable1 = variable1 ;

so my problem solved but by changing RTL always functionality should meet

• setup violations are more dangerous error then hold violations which must be solved during synthesis

1. try to change logic of ur code
2. try to change cells drives in netlist
3. try to avoid delay cells
4. try to reduce ur setup constrains from 20 to less then 20 percentage if it does not required much
5. if ur functionality not effects much if logic is meeting for second clock pulse then go for multicycle path
6. put false paths between two clocks if ur design using two clocks

• hold violations can be done in back end by changing RC values , but during synthesis also u can remove with command "set_fix_hold"

which automatically puts buffers in data path , if not solved put manual delay buffers in the netlist

so, i shared my experience

regards

vijay

Verilog Interview Questions

• What is the difference between $display and $monitor and $write and $strobe?
• What is the difference between code-compiled simulator and normal simulator?
• What is the difference between wire and reg?
• What is the difference between blocking and non-blocking assignments?
• What is the significance Timescale directivbe?
• What is the difference between bit wise, unary and logical operators?
• What is the difference between task and function?
• What is the difference between casex, casez and case statements?
• Which one preferred-casex or casez?
• For what is defparam used?
• What is the difference between “= =” and “= = =” ?
• What is a compiler directive like ‘include’ and ‘ifdef’?
• Write a verilog code to swap contents of two registers with and without a temporary register?
• What is the difference between inter statement and intra statement delay?
• What is delta simulation time?
• What is difference between Verilog full case and parallel case?
• What you mean by inferring latches?
• How to avoid latches in your design?
• Why latches are not preferred in synthesized design?
• How blocking and non blocking statements get executed?
• Which will be updated first: is it variable or signal?
• What is sensitivity list?
• If you miss sensitivity list what happens?
• In a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk? If yes, why? If not, why?
• In a pure sequential circuit is it necessary to mention all the inputs in sensitivity disk? If yes, why? If not, why?
• What is general structure of Verilog code you follow?
• What are the difference between Verilog and VHDL?
• What are system tasks?
• List some of system tasks and what are their purposes?
• What are the enhancements in Verilog 2001?
• Write a Verilog code for synchronous and asynchronous reset?
• What is pli? why is it used?
• What is file I/O?
• What is difference between freeze deposit and force?
• Will case always infer priority register? If yes how? Give an example.
• What are inertial and transport delays ?
• What does `timescale 1 ns/ 1 ps’ signify in a verilog code?
• How to generate sine wav using verilog coding style?
• How do you implement the bi-directional ports in Verilog HDL?
• How to write FSM is verilog?
• What is verilog case (1)?
• What are Different types of Verilog simulators available?
• What is Constrained-Random Verification ?
• How can you model a SRAM at RTL Level?

Clock Uncertainity

Clock Definitions

Rising and falling edge of the clock

For a +ve edge triggered design +ve (or rising) edge is called ‘leading edge’ whereas –ve (or falling) edge is called ‘trailing edge’.

For a -ve edge triggered design –ve (or falling) edge is called ‘leading edge’ whereas +ve (or rising) edge is called ‘trailing edge’.

basic clock

Minimum pulse width of the clock can be checked in PrimeTime by using commands given below:

set_min_pulse_width -high 2.5 [all_clocks]

set_min_pulse_width -low 2.0 [all_clocks]

These checks are generally carried out for post layout timing analysis. Once these commands are set, PrimeTime checks for high and low pulse widths and reports any violations.

Capture Clock Edge

The edge of the clock for which data is detected is known as capture edge.

Launch Clock Edge

This is the edge of the clock wherein data is launched in previous flip flop and will be captured at this flip flop.

launch clock and capture clock

Skew

Skew is the difference in arrival of clock at two consecutive pins of a sequential element is called skew. Clock skew is the variation at arrival time of clock at destination points in the clock network. The difference in the arrival of clock signal at the clock pin of different flops.

Two types of skews are defined: Local skew and Global skew.

Local skew

Local skew is the difference in the arrival of clock signal at the clock pin of related flops.

Global skew

Global skew is the difference in the arrival of clock signal at the clock pin of non related flops. This also defined as the difference between shortest clock path delay and longest clock path delay reaching two sequential elements.

local and global skew

Skew can be positive or negative. When data and clock are routed in same direction then it is Positive skew. When data and clock are routed in opposite direction then it is negative skew.

Positive Skew

If capture clock comes late than launch clock then it is called +ve skew.

Clock and data both travel in same direction.

When data and clock are routed in same direction then it is Positive skew.

+ve skew can lead to hold violation.

+ve skew improves setup time.

positive skew negative skew

Negative Skew

If capture clock comes early than launch clock it is called –ve skew. Clock and data travel in opposite direction. When data and clock are routed in opposite then it is negative skew. -ve skew can lead to setup violation. -ve skew improves hold time. (Effects of skew on setup and hold will be discussed in detail in forthcoming articles)

Uncertainty

Clock uncertainty is the time difference between the arrivals of clock signals at registers in one clock domain or between domains.

Pre-layout and Post-layout Uncertainty

Pre CTS uncertainty is clock skew, clock Jitter and margin. After CTS skew is calculated from the actual propagated value of the clock. We can have some margin of skew + Jitter.

timing diagram depicting skew, latency, jitter

Clock latency

Latency is the delay of the clock source and clock network delay.

Clock source delay is the time taken to propagate from ideal waveform origin point to clock definition point. Clock network latency is the delay from clock definition point to register clock pin.

Pre CTS Latency and Post CTS Latency

Latency is the summation of the Source latency and the Network latency. Pre CTS estimated latency will be considered during the synthesis and after CTS propagated latency is considered.

Source Delay or Source Latency

It is known as source latency also. It is defined as "the delay from the clock origin point to the clock definition point in the design".

Delay from clock source to beginning of clock tree (i.e. clock definition point).

The time a clock signal takes to propagate from its ideal waveform origin point to the clock definition point in the design.

Network Delay (latency) or Insertion Delay

It is also known as Insertion delay or Network latency. It is defined as "the delay from the clock definition point to the clock pin of the register".

The time clock signal (rise or fall) takes to propagate from the clock definition point to a register clock pin.

Figure below shows example of latency for a design without PLL.

latency for a design without PLL

The latency definitions for designs with PLL are slightly different.

Figure below shows latency specifications of such kind of designs.

Latency from the PLL output to the clock input of generated clock circuitry becomes source latency. From this point onwards till generated clock divides to flops is now known as network latency. Here we can observe that part of the network latency is clock to q delay of the flip flop (of divide by 2 circuit in the given example) is known value.

latency for a design with PLL

Jitter

Jitter is the short-term variations of a signal with respect to its ideal position in time.

Jitter is the variation of the clock period from edge to edge. It can vary +/- jitter value.

From cycle to cycle the period and duty cycle can change slightly due to the clock generation circuitry. Jitter can also be generated from PLL known as PLL jitter. Possible jitter values should be considered for proper PLL design. Jitter can be modeled by adding uncertainty regions around the rising and falling edges of the clock waveform.

Sources of Jitter Common sources of jitter include:

• Internal circuitry of the phase-locked loop (PLL)

• Random thermal noise from a crystal

• Other resonating devices

• Random mechanical noise from crystal vibration

• Signal transmitters

• Traces and cables

• Connectors

• Receivers

Multiple Clocks

If more than one clock is used in a design, then they can be defined to have different waveforms and frequencies. These clocks are known as multiple clocks. The logics triggered by each individual clock are then known as “clock domain”.

If clocks have different frequencies there must be a base period over which all waveforms repeat.

Base period is the least common multiple (LCM) of all clock periods

Asynchronous Clocks

In multiple clock domains, if these clocks do not have a common base period then they are called as asynchronous clocks. Clocks generated from two different crystals, PLLs are asynchronous clocks. Different clocks having different frequencies generated from single crystal or PLL are not asynchronous clocks but they are synchronous clocks.

Gated clocks

Clock signals that are passed through some gate other than buffer and inverters are called gated clocks. These clock signals will be under the control of gated logic. Clock gating is used to turn off clock to some sections of design to save power. Click here to read more about clock gating.

Generated clocks

Generated clocks are the clocks that are generated from other clocks by a circuit within the design such as divider/multiplier circuit.

Static timing analysis tools such as PrimeTime will automatically calculate the latency (delay) from the source clock to the generated clock if the source clock is propagated and you have not set source latency on the generated clock.

generated clock

‘Clock’ is the master clock and new clock is generated from F1/Q output. Master clock is defined with the constraint ‘create_clok’. Unless and until new generated clock is defined as ‘generated clock’ timing analysis tools won’t consider it as generated clock. Hence to accomplish this requirement use “create_generated_clock” command. ‘CLK’ pin of F1 is now treated as clock definition point for the new generated clock. Hence clock path delay till F1/CLK contributes source latency whereas delay from F1/CLK contributes network latency.

Virtual Clocks

Virtual clock is the clock which is logically not connected to any port of the design and physically doesn’t exist. A virtual clock is used when a block does not contain a port for the clock that an I/O signal is coming from or going to. Virtual clocks are used during optimization; they do not really exist in the circuit.

Virtual clocks are clocks that exist in memory but are not part of a design. Virtual clocks are used as a reference for specifying input and output delays relative to a clock. This means there is no actual clock source in the design. Assume the block to be synthesized is “Block_A”. The clock signal, “VCLK”, would be a virtual clock. The input delay and output delay would be specified relative to the virtual clock.